It is known, for example, to incorporate a shift register in the feedback loop of an arithmetic logic unit, so to provide a circuit that can perform ADD-then-SHIFT operations. By way of example a typical arrangement is shown in FIG. 1. Here, a 4-bit parallel binary accumulator is shown in which a shift register 1 is interposed in the path between the output of an arithmetic logic unit 3 and one of its inputs. It is noted that for the configuration shown, data can be shifted only one bit at a time and that for 16-bit data signal processing a number of such devices have to be connected in cascade.
In an alternative known arrangement, shown in FIG. 2, a 16-bit barrel shifter 5 is provided at one input of the arithmetic logic unit 3. This circuit includes an accumulating register 7 and a 16-bit data latch 9 each of which is connected in parallel to the output of the arithmetic logic unit 3 and to the circuit data input by means of a two-way connective path. The outputs from the register 7 and from the latch are selected and referred to the remaining input of the arithmetic logic unit 3 and the barrel shifter 5 by controlled multiplexers 11 and 13. It is noted that in this configuration only SHIFT-then-ADD operation is afforded, the barrel shifter will operate but once to perform a 16-bit shift, and that the arithmetic logic unit and barrel shifter operations are interdependent.
A known and more versatile combination of arithmetic logic circuit and barrel shifter is shown in FIG. 3. In this combination the arithmetic logic unit 3 and the barrel shifter 5 are each followed by a register 15, 17 and the output of each register is channeled onto a common feedback line 19 by means of a first multiplexer 21. A further multiplexer 23 and an output enable gate 25 is also connected in parallel to the first multiplexer 21 so that signal may be channeled to the device output. Data input signals X, Y, as also feedback signal channeled via the first multiplexer 21, are channeled to the inputs of the arithmetic logic unit 3 and barrel shifter 5 by means of a network of yet further multiplexers 27 to 37, some six in number. This device is capable of both SHIFT-then-ADD and ADD-then-SHIFT operations and furthermore the arithmetic logic unit 3 and barrel shifter 5 may be operated independently. However, a particular disadvantage of this configuration is that it requires not one but two clock cycles in order to feedback the contents of both registers 15, 17. Thus SHIFT-AND-ACCUMULATE operation is relatively slow and is less than wholly satisfactory for high performance applications. The inordinately large number of multiplexers--i.e. high parts count, is likewise noted.